1. Field of the Invention
The present invention relates to circuit routing, for example, but not exclusively to routing an integrated circuit.
2. Discussion of the Related Art
Electronic Design Automation (EDA) is the use of a series of tools to assist the creation of circuits such as integrated circuits (IC) or field programmable gate array (FPGA) circuits. These tools can assist automation of the design process and can attempt to produce a global optimization of the routing and positioning of the elements and components of the circuit under design. However on chip variations (OCV) require that the designs have ‘pessimism’ introduced to account for any variations in the integrated circuit. Also pessimism is introduced to account for any correlation differences between the tools used for implementation and Signoff. These ‘pessimism’ elements can be considered to be for example a series of extra margins such as increased uncertainties and derations applied to timings.
Furthermore as circuits are designed using smaller components the extra margins required increases as, for example hold violations, examples where output data is not held for long enough and may pass through multiple stages and thus destroy signal integrity at a later stage or process, relatively increase. For example in 65 nm process technology we have approximately 5% deration on launch/capture clock components, and 10% data deration whereas for a 32 nm process the occurrences are 6% deration on launch/capture clock and 18% data deration. These figures may vary for different processes and different foundries.
Typically hold violations are targeted during the design stage by adding additional buffer or delay elements. However such approaches have problems such as degrading the set-up time, creating congestion hot-spots, increasing overall design utilization, increased cycle time for design closure and possible voltage drop across the circuit also known as IR drop caused by the additional components.
Furthermore although a significant number of hold violations violate the timing constraints by only a few picoseconds the buffers typically add a much greater delay than is required. For example a buffer in 65 nm process technology can generate a 20-25 ps delay and be used to implement a delay for a hold violation of as little as 1 ps.
Other proposed methods to fix hold time violations are to increase wire length by scan chain reordering, or to reorder the scan chain depending upon local clock skew which favours hold time. However these methods can only be applied to shift mode hold violations and so are not suitable for other modes of operation such as functional modes of operation, built in self test modes of operation or capture modes.